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features ? serial peripheral inte rface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) ? datasheet describe s mode 0 operation 50 mhz clock rate byte mode and page mode progra m (1 to 256 bytes) operations sector/block/page architecture ? sixteen 256 byte pages per sector ? sixteen 4 kbyte sectors per block ? eight uniform 64 kbyte blocks self-timed sector, block and chip erase product identifi cation mode with jedec standard low-voltage operation ?2.7v (v cc = 2.7v to 3.6v) hardware and software write protection ? device protection with write protect (wp ) pin ? write enable and write disable instructions ? software write protection: upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or entire array flexible op codes for maximum compatibility self-timed program cycle ? 30 s/byte typical single cycle reprogramming (erase and program) for status register high reliability ? endurance: 10,000 write cycles typical 8-lead jedec 150mil soic and 8-lead ultra thin small ar ray package (sap) die sales: waffer form, tape and reel, and bumped wafers description the at25fs040 provides 4,194,304 bits of serial reprogrammable flash memory organized as 524,288 words of 8 bits each . the device is optimized for use in many industrial and commercial applications w here low-power and low-voltage operation are essential. the at25fs040 is available in a space-saving 8-lead jedec soic and 8-lead ultra thin sap packages. table 0-1. pin configuration pin name function cs chip select sck serial data clock si serial data input so serial data output gnd ground vcc power supply wp write protect hold suspends serial input high speed small sectored spi flash memory 4m (524,288 x 8) at25fs040 5107e?sflsh?8/07 8-lead jedec soic 1 2 3 4 8 7 6 5 cs so wp gnd vcc hold sck si 8-lead sap 1 2 3 4 8 7 6 5 vcc hold sck si cs so wp gnd __ _ __ _ _ ____ bottom view
2 5107e?sflsh?8/07 at25fs040 the at25fs040 is enabled through the chip select pin (cs ) and accessed via a 3-wire inter- face consisting of serial data input (si), serial data output (so), and serial clock (sck). all write cycles are completely self-timed. block write protection for upper 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 or the entire memory array is enabled by programming the status register. separate write enable and write disable instruc- tions are provided for additional data protection. hardware data protection is provided via the wp pin to protect against inadvertent write attempts to the status register. the hold pin may be used to suspend any serial communication without resetting the serial sequence. figure 1-1. block diagram 1. absolute maximum ratings* operating temperature....................................?40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .....................................?65 c to +150 c voltage on any pin with respect to ground .................................... ?1.0v to +5.0v maximum operating voltage ............................................ 4.2v dc output current........................................................ 5.0 ma 524,288 x 8
3 5107e?sflsh?8/07 at25fs040 note: 1. this parameter is characterized and is not 100% tested. note: 1. v il and v ih max are reference only and are not tested. table 1-1. pin capacitance (1) applicable over recommended operating range from t a = 25 c, f = 1.0 mhz, v cc = +3.6v (unless otherwise noted) symbol test conditions max units conditions c out output capacitance (so) 8 pf v out = 0v c in input capacitance (cs , sck, si, wp , hold )6pfv in = 0v table 1-2. dc characteristics (prelimin ary ? subject to change) applicable over recommended operating range from: t ai = ? 40 c to +85 c, v cc = +2.7v to +3.6v, t ac = 0 c to +70 c, v cc = +2.7v to +3.6v (unless otherwise noted) symbol parameter test co ndition min typ max units v cc supply voltage 2.7 3.6 v i cc1 supply current v cc = 3.6v at 20 mhz, so = open read 10.0 17.0 ma i cc2 supply current v cc = 3.6v at 20 mhz, so = open write 15.0 45.0 ma i sb standby current v cc = 2.7v, cs = v cc 2.0 10.0 a i il input leakage v in = 0v to v cc -3.0 3.0 a i ol output leakage v in = 0v to v cc , t ac = 0 c to 70 c -3.0 3.0 a v il (1) input low voltage -0.6 v cc x 0.3 v v ih (1) input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage 2.7v v cc 3.6v i ol = 0.15 ma 0.2 v v oh output high voltage i oh = -100 a v cc - 0.2 v
4 5107e?sflsh?8/07 at25fs040 notes: 1. the programming time for n bytes will be equal to n x t bpc . 2. this parameter is characterized at 3.0v. 3. one write cycle consists of erasing a sector , followed by programming the same sector. table 1-3. ac characteristics (preliminary ? subject to change) applicable over recommended operating range from t a = ? 40 c to +85 c, v cc = +2.7v to +3.6v c l = 1 ttl gate and 30 pf (unless otherwise noted) symbol parameter min typ max units f sck sck clock frequency 0 50 mhz t ri input rise time 5 ns t fi input fall time 5 ns t wh sck high time 9 ns t wl sck low time 9 ns t cs cs high time 100 ns t css cs setup time 5 ns t csh cs hold time 5 ns t su data in setup time 5 ns t h data in hold time 5 ns t hd hold setup time 5 ns t cd hold hold time 5 ns t v output valid 9ns t ho output hold time 0 ns t lz hold to output low z 9 ns t hz hold to output high z 9 ns t dis output disable time 9 ns t se sector erase time 50 200 ms t be block erase time 200 500 ms t ce chip erase time 1.6 4 s t sr status register write cycle time 60 ms t bpc byte program cycle time (1) 30 50 s endurance (2) 10k write cycles (3)
5 5107e?sflsh?8/07 at25fs040 2. serial interface description master: the device that generates the serial clock. slave: because the serial clock pin (sck) is always an input, the at25fs040 always oper- ates as a slave. transmitter/receiver: the at25fs040 has separate pins designated for data transmis- sion (so) and reception (si). msb: the most significant bit (msb) is the first bit transmitted and received. serial op-code: after the device is selected with cs going low, the first byte will be received. this byte contains the op-code that defines the operations to be performed. invalid op-code: if an invalid op-code is received, no data will be shifted into the at25fs040, and the serial output pin (so) will rema in in a high impedanc e state until the falling edge of cs is detected again. this will rein itialize the serial communication. chip select: the at25fs040 is selected when the cs pin is low. when the device is not selected, data will not be accepted vi a the si pin, and the serial ou tput pin (so) will remain in a high impedance state. hold: the hold pin is used in conjunction with the cs pin to select the at25fs040. when the device is selected and a serial sequence is underway, hold can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, the hold pin must be brought low while the sck pin is low. to resume serial communication, the hold pin is brought high while the sck pin is low (sck may still toggle during hold ). inputs to the si pin will be ignored while the so pin is in the high impedance state. write protect: the at25fs040 has a write lockout feature that can be activated by assert- ing the write protect pin (wp ). when the lockout feature is activated, locked-out sectors will be read only. the write protect pin will allow no rmal read/write operations when held high. when the wp is brought low and wpen bit is ?1?, all write operations to the status register are inhib- ited. wp going low while cs is still low will interrupt a write to the status register. if the internal status register write cycle has already been initiated, wp going low will have no effect on any write operation to the status register. the wp pin function is blocked when the wpen bit in the status register is ?0?. this will allow the user to install the at25fs040 in a system with the wp pin tied to ground and still be able to write to the status register. all wp pin functions are enabled when the wpen bit is set to ?1?.
6 5107e?sflsh?8/07 at25fs040 3. operating features 3.1 recommended power-up when the power supply is turned on, the vcc to the device rises monotonically from ground to the full operating vcc. during this time, the chip select (cs) signal is not allowed to float and must follow vcc. for this reason, it is recommended to use a suitable pull-up resistor connected between cs and vcc. the device is ready for communication once a stable vcc is reached within the specified operating voltage range. 3.2 recommended power-down the device must be deselected and in standby and write disabled mode prior to vcc power down sequence. this means there should be no write oper ation/internal write cycle or read operation in progress during power down. the vcc decay should be monotonic from vcc to ground and the chip select (cs) line must be allowed to follow vcc during power down. after power down, it is recommended vcc should be held at ground level for at least 0.5 seconds before power up again. 3.3 power on reset protection in order to prevent data corruption and inadvertent write operations during device power-up and power down, a power on reset (por) circuit is enabled. at power-up (continuous rise of vcc from 0v), the device will not respond to any inst ruction and will be held in reset (which puts the device in standby mode) until the vcc has reached the power on reset threshold voltage. this threshold is lower than the minimum specified vcc operating voltage. at power down (continuous fall of vcc), when vcc drops from the operating voltage below the por threshold, all operations are disabled and the device will not respond to any command. a stable and valid vcc must be applied bef ore executing any communication. please note: the por threshold trip point is ~1.8v for serial flash products and is ensured by design to have a reset during power-up and power down and is not 100% tested.
7 5107e?sflsh?8/07 at25fs040 figure 3-1. spi serial interface master: microcontroller slave: at25fs040 data out (mosi) data in (miso) serial clock (spi ck) ss0 ss1 ss2 ss3 si so sck cs si so sck cs si so sck cs si so sck cs
8 5107e?sflsh?8/07 at25fs040 4. functional description the at25fs040 is designed to interface directly with the synchronous serial peripheral interface (spi) of the 6800 type series of microcontrollers. the at25fs040 utilizes an 8-bit instruction register. the list of instructions and their operation codes are contained in table 4-1 . all instructions, addresses, and data are transferred with the msb first and start with a high-to-low transition. write is defined as program and/or erase in this specification. the following commands, pro- gram, sector erase, block erase, chip era se, and wrsr are write instructions for at25fs040. note: 1. either one of the op codes will execute the instruction. write enable (wren): the device will power up in the write disable state when v cc is applied. all write instructions must therefore be preceded by the wren instruction. write disable (wrdi): to protect the device against inadvertent writes, the wrdi instruc- tion disables all write commands. the wrdi inst ruction is independent of the status of the wp pin. read status register (rdsr): the rdsr instruction provides access to the status regis- ter. the ready/busy and write enable status of the device can be determined by the rdsr instruction. similarly, the block write protection bits indicate the extent of protection employed. table 4-1. instruction set for the at25fs040 instruction name one byte opcode operation binary hex wren 0000 x110 06 set write enable latch wrdi 0000 x100 04 reset write enable latch rdsr 0000 x101 05 read status register wrsr 0000 x001 01 write status register read 0000 0011 03 read data from memory array fast read 0000 1011 0b read data from me mory array (with dummy cycles) program 0000 x010 02 program data into memory array sector erase (1) 0010 0000 20 erase one 4kbyte sector in memory array 1101 0111 d7 block erase(1) 0101 0010 52 erase one 64kbyte block in memory array 1101 1000 d8 chip erase(1) 0110 0000 60 erase all memory array 1100 0111 c7 rdid(1) 1001 1111 9f read manufacturer and product id 1010 1011 ab
9 5107e?sflsh?8/07 at25fs040 these bits are set by using the wrsr instruction. during internal write cycles, all other com- mands will be ignored except the rdsr instruction. read product id (rdid): the rdid instruction allows the user to read the manufacturer id byte followed by two device id bytes. the manufa cturer id is assigned by jedec and is 1fh for atmel (see table 4-4 ). the first device id byte indicate s the memory type (66h=at25fs040) fol- lowed by the device memory capac ity byte (04h). for maximum co mpatibility and flexibility, two rdid opcodes (9fh and abh) are supported and will pe rform the same operation. the device is first selected by driving chip select (cs ) low then the rdid opcode is shifted in on serial in (si) during rising edge of clock. the 24-bit manufacturer and device identification codes stored in memory are clocked out on serial output (so) starting on the falling edge of clock (see figure 5-13 ). if cs stays low after the last bit of second device id byte is shifted out, the manufacturer id and 2 byte device id will continue to be clocked out until cs goes high. the rdid sequence is terminated any time cs is driven high and the device will go into standby mode. write status register (wrsr): the wrsr instruction allows the user to select one of eight levels of protection for the at25fs040. the at25fs040 is divided into eight blocks where the top 1/64, 1/32, 1/16, 1/8, top quarter (1/4), top half (1/2), or all of the memory blocks can be protected (locked out) from writ e. any of the locked-out blocks will therefore be read only. the locked-out sector/block and the corresponding status register control bits are shown in table 4-5 on page 10 . table 4-2. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wpen bp4 bp3 bp2 bp1 bp0 wen rdy table 4-3. read status register bit definition bit definition bit 0 (rdy ) bit 0 = 0 (rdy ) indicates the device is ready. bit 0 = 1 indicates the write cycle is in progress. bit 1 (wen) bit 1 = 0 indicates the device is not write enabled. bit 1 = 1 indicates the device is write enabled. bit 2 (bp0) see table 4-5 . bit 3 (bp1) see table 4-5 . bit 4 (bp2) see table 4-5 . bit 5 (bp3) see table 4-5 . bit 6 (bp4) see table 4-5 . bit 7 (wpen) see table 4-6 . bits 0-7 are 1s during an internal write cycle. table 4-4. read product id (rdid) manufacturer id device id memory type memory capacity 1fh 66h 04h
10 5107e?sflsh?8/07 at25fs040 the six bits, bp0, bp1, bp2, bp3, bp4 and wpen, are nonvolatile cells that have the same properties and functions as the regular memory cells. note: 1. x = don?t care the wrsr instruction also allows the user to enable or disable the write protect (wp ) pin through the use of the write protect enable (wpen) bit. hardware write protection is enabled when the wp pin is low and the wpen bit is ?1?. ha rdware write protection is disabled when either the wp pin is high or the wpen bit is ?0.? when the device is hardware write protected, writes to the status register, including the block protect bits and the wpen bit, and the locked- out sectors in the memory array are disabled. write is only allowed to sectors of the memory which are not locked out. the wrsr instruction is self-timed to automatically erase and pro- gram bp0, bp1, bp2, bp3, bp 4 and wpen bits. in order to write the status register, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then, cs must be low and the wrsr instruction and data for the six bits are entered. the wrsr writ e cycle will begin once cs goes high. during the internal write cycle, all instructions will be ignored exce pt rdsr instructions . the at25fs040 will automatically return to write disable state at the completion of the wrsr cycle. the status register is factory pro- grammed to all 0?s. note: when the wpen bit is hardware write protected, it cannot be changed back to ?0?, as long as the wp pin is held low. table 4-5. sector/block write protect bits level status register bits at25fs040 bp4 bp3 bp2 bp1 bp0 array address locked out locked-out blocks 0(none)0 0000none none 1(1/64) 0 100007e000h - 07ffffhsector 15-16 of block 8 2(1/32) 1 000007c000h - 07ffffhsector 13-16 of block 8 3(1/16) 1 1000 078000h - 07ffffh sector 9-16 of block 8 4(1/8) x x 0 0 1 070000h - 07ffffh all sectors of block 8 5(1/4) x x 0 1 0 060000h - 07ffffh al l sectors of block 7,8 6(1/2) x x 0 1 1 040000h - 07ffffh all sectors of block 5,6,7,8 7(all) x x 1 x x 000000h - 07ffffh all sectors of all blocks (1-8) table 4-6. wpen operation wpen wp wen protectedblocks unpr otectedblocks status register 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable
11 5107e?sflsh?8/07 at25fs040 read (read): the read instruction sequence reads the memory array up to the maximum speed of 50mhz. reading the at25fs040 via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select the devi ce, the read instru ction is clocked in on the si line, followed by the byte address to be read. upon completion, any data on the si line will be ignored. the data (d7-d0 ) at the specified address is t hen shifted out onto the so line (see figure 5-6 ). if only one byte is to be read, the cs line should be driven high after the least significant data bit. to continue read op eration and sequentially read subsequent byte addresses from the device by simply keeping cs low and provide a clock signal. the device incorporates an internal address counter that automatically increments to the next byte address during sequential read operation. the read in struction can be cont inued since the byte address is automatically incremented and data will continue to be shifted out of the at25fs040 until the highest byte address is reached. when the last bit of the memory has been read, the device will continue reading bac k at the beginning of the array (000000h) without delay. the data is always output from the device with the mo st significant bit (msb) of a byte first. the read sequence is te rminated any time cs is driven high and the de vice will go into standby mode. fast read (fast read): the fast read instruction sequence reads the memory array up to the maximum speed of 50mhz (same as st andard read sequence). the fast read is an alternate command for the read and allows for fast read instruction compatibility support. the difference between the two is fast read requires a ?dummy byte? and read does not. reading the at25fs040 via the so (serial output) pin requires the following sequence. after the cs line is pulled low to select the device, the fa st read instruction is clocked in on the si line, followed by the byte addre ss to be read and the dummy byte (the so line output will be high z state). upon completion, any da ta on the si line will be ignored. the data (d7-d0 ) at the spec- ified address is then shifted out onto the so line (see figure 5-7 ). if only one byte is to be read, the cs line should be driven high after the least significant data bit. to continue read operation and sequentially read subsequent byte addresse s from the device by simply keeping cs low and provide a clock signal. the device incorporates an internal address counter that automati- cally increments to the next byte address during sequential read operation. the fast read instruction can be continued since the byte address is automatically incremented and data will continue to be shifted out of the at25fs040 until the highest address is reached. when the last bit of the memory has been read, the device will continue reading back at the beginning of the array (000000h) without delay. the data is always output from the device with the most signifi- cant bit (msb) of a byte first. the fast read sequence is terminated any time cs is driven high and the device will go into standby mode. program (program): the program instruction allows up to 256 data bytes to be written to each page in the memory in one-operation changing data bits from a logic 1 to 0 state. the at25fs040 memory array contains 524,288 programmable data bytes internally organized into 256 bytes per page with a total of 2048 pages in the memory. in order to program the at25fs040, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then the program instruction can be executed and requires the following sequence. after the cs line is pulled low to select the device, the program instruction is clocked in via the si line followed by the byte address (see figure 5-8 ) and the data byte(s) to be programmed. programming will start after cs pin is brought high. please note: the low to high transition of the cs pin must occur during the sck low time immediately after clocking in the d0 (lsb) data bit to initiate programming cycle. also, a wren instruction must precede each and every program instruction. the ready/busy status of the device can be determined by initiating a rdsr instruction. if bit 0=1, the program cycle is
12 5107e?sflsh?8/07 at25fs040 still in progress. if bit 0=0, the programming cycle has ended. only the rdsr instruction is enabled during the programming cycle and all other opcode instructions are ignored until pro- gramming cycle has completed. a single program instruction programs 1 to 256 consecutive bytes within a page if it is not write protected. the starting byte address can be anywhere within the page. when the end of the page is reache d, the address will wrap around to the beginning of the same page. if the data to be programmed is less than a full page, the data of all ot her bytes on the same page will remain unchanged meaning that the unwritten addr ess locations within the page will not be changed. if more than 256 bytes of data are provided, the address counter will roll over on the same page and the prev ious data provided will be replac ed. the same byte cannot be repro- grammed without erasing the whole sector or block first. the at25fs040 will automatically return to the write disable state at the completion of the programming cycle. note: if the device is not write enabled (wren), th e device will ignore the write instruction and will return to the standby state when cs is brought high. a new cs falling edge is required to re-ini- tiate the serial communication. erase operation: the at25fs040 memory array is internally organized into uniform 4k byte sectors or uniform 64k byte uniform blocks (see table 4-8 ). before data can be reprogrammed, the sector or block that contains the data must be erased first. in order to erase the at25fs040, there are three flexible erase instructions that can be executed as follows: sector erase, block erase and chip erase instructions. a sector erase instruction allows erasing any individua l 4k sector without changing data in rest of memory. the block erase instruction allo ws erasing any individual block and chip erase allows erasing the entire memory array. sector erase (sector erase): the sector erase instruction sets all 4k bytes in the selected sector to logic 1 or erased state. in order to sector erase the at25fs040, two separate instructions must be executed. first, the device must be write enabled via the wren instruction. then the sector erase instructi on can be executed and will erase every byte in the selected sector if the sector is not locked out. the sector address is automatically determined if any address within the sector is selected (see figure 5-10 ). the sector erase instruction is internally controlled and self ti med to completion. during this time, all commands will be ignored except rdsr instruction. the progress or completion of the erase operation can be determined by reading ready/busy bit (bit 0) through rdsr instruction. if bit 0=1, sector erase cycle is in progress. if bit 0=0, the erase operation has been completed. the at 25fs040 will automatically return to the write disable state at the completion of the sector erase cycle. table 4-7. address key address at25fs040 a n a 18 - a 0 don?t care bits a 23 - a 19
13 5107e?sflsh?8/07 at25fs040 table 4-8. sector and block address block 8 1/8 1/16 1/32 1/64 sector 16 07ffffh 07f000h sector 15 07efffh 07e000h sector 14 07dfffh 07d000h sector 13 07cfffh 07c000h sector 12 07bfffh 07b000h sector 11 07afffh 07a000h sector 10 079fffh 079000h sector 9 078fffh 078000h sector 8 077fffh 077000h sector 7 076fffh 076000h sector 6 075fffh 075000h sector 5 074fffh 074000h sector 4 073fffh 073000h sector 3 072fffh 072000h sector 2 071fffh 071000h sector 1 070fffh 070000h block 7 06ffffh 060000h block 6 05ffffh 050000h
14 5107e?sflsh?8/07 at25fs040 block erase (block erase): the block era se instruction sets all 64k bytes in the selected block to logic 1 or erased state. in order to block erase the at25fs040, two sep- arate instructions must be executed. first, the device must be write enabled via the wren instruction. then the block erase in struction can be executed and will erase every byte in the selected block if the block is not locked out. the block address is auto- matically determined if any address within the block is selected (see figure 5-11 ). the block erase instruction is internally cont rolled and self timed to completion. during this time, all commands will be ignored ex cept rdsr instruction. the progress or com- pletion of the erase operation can be determined by reading ready/busy bit (bit 0) through rdsr instruction. if bit 0=1, block erase cycle is in progress. if bit0=0, the erase opera- tion has been completed. the at25fs040 will automatically return to the write disable state at the completion of the block erase cycle. chip erase (chip erase): as an alternative to the se ctor erase/block erase, the chip erase instruction will erase every byte in all sectors that are not locked out. first, the device must be write enabled via the wren instruction. then the chip erase instruction can be executed. the chip erase instruction is inter nally controlled; it will automatically be timed to completion. the chip erase cycle time typica lly is 4 seconds. during the internal erase cycle, all instructions will be ignored except rdsr. the at25fs040 will automatically return to the write disable state at the co mpletion of the chip erase cycle. block 5 04ffffh 040000h block 4 03ffffh 030000h block 3 02ffffh 020000h block 2 01ffffh 010000h block 1 00ffffh 000000h table 4-8. sector and block address (continued)
15 5107e?sflsh?8/07 at25fs040 5. timing diagrams (for spi mode 0 (0, 0)) figure 5-1. synchronous data timing figure 5-2. wren timing figure 5-3. wrdi timing v oh v ol hi-z hi-z t v valid in v ih v il t h t s u t di s v ih v il t wh t c s h v ih v il t c ss t c s t wl t ho cs sck si so hi-z wren op-code 0 1 2 3 4 5 6 7 c s s ck s i s o c s s ck s i s o wrdi op-code hi-z 0 1 2 3 4 5 6 7
16 5107e?sflsh?8/07 at25fs040 figure 5-4. rdsr timing figure 5-5. wrsr timing figure 5-6. read timing cs sck 0123456789101112131415 si so 76543210 msb rdsr op-code high impedance data out high impedance data in wr s r op-code 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 c s s ck s i s o cs si sck high impedance address bits a23 - a0 01234 d 5 d 6 d 7 d 8 9 10 11 12 ... aa dd a 29 30 31 32 33 34 35 36 37 38 39 40 so ... a a 1 1aaaa 0 00000 msb msb msb msb opcode dd dd
17 5107e?sflsh?8/07 at25fs040 figure 5-7. fast read timing figure 5-8. program timing figure 5-9. hold timing cs si sck high impedance address bits a23 - a0 don?t care 01 234 d 5 d 6 d 7 d 8 9 10 11 12 ... aa dd a 29 30 31 32 33 34 35 36 37 38 39 40 so 41 42 43 44 45 46 47 48 ... a a 1 1aaaa 0 00000 x x x xxxxx msb msb msb msb msb opcode dd dd data byte 1 c s s ck s i s o 3 -byte addre ss 1 s t byte data-in 256th byte data-in high impedance 012 3 4567 8 9 10112 8 2 3 22 21 3 10 654 3 210 7 2 29 3 0 3 1 3 2 33 3 4 2075 2076 207 8 2077 2079 program op-code t cd t hd t hz t lz t cd t hd c s s ck hold s o
18 5107e?sflsh?8/07 at25fs040 figure 5-10. sector erase timing figure 5-11. block erase timing figure 5-12. chip erase timing c s s ck s i s o 0 1 2 3 4 5 6 7 8 9 10 11 2 8 29 3 0 3 1 3 -byte addre ss high impedance 2 3 22 21 3 2 1 0 s ector era s e op-code block era s e op-code c s s ck s i s o 0 1 2 3 4 5 6 7 8 9 10 11 2 8 29 3 0 3 1 3 -byte addre ss high impedance 2 3 22 21 3 2 1 0 chip era s e op-code high impedance 0 1 2 3 4 5 6 7 c s s ck s i s o
19 5107e?sflsh?8/07 at25fs040 figure 5-13. rdid timing 12 13 14 15 16 17 18 31 cs sck si so 0 1 2 3 4 5 6 7 8 910 11 high impedance 28 29 30 data out 15 14 3 21 0 66 04 manufacturer code (atmel = 1f) rdid op-code
20 5107e?sflsh?8/07 at25fs040 notes: 1. ?-b? denotes bulk. 2. ?-t? denotes tape and reel, soic = 4k per re el and sap = 3k per reel. ordering information ordering code volltage package operation range AT25FS040N-SH27-B (1) 2.7 8s1 lead-free/halogen-free/ nipdau lead finish industrial temperature (?40 c to 85 c) at25fs040n-sh27-t (2) 2.7 8s1 at25fs040y7-yh27-t (2) 2.7 8y7 package type 8s1 8-lead, 0.150? wide, plastic gull wing small outline (jedec soic) 8y7 8-lead, 6.00 mm x 4.90 mm body, ultra thin, dual footprint, non-leaded, small array package (sap) options ?2.7 low voltage (2.7v to 3.6v)
21 5107e?sflsh?8/07 at25fs040 6. part marking scheme 6.1 8-soic 6.2 8-ultra thin sap top mark seal year y = seal year ww = seal week | seal week 6: 2006 0: 2010 02 = week 2 | | | 7: 2007 1: 2011 04 = week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: : a t m l h y w w 9: 2009 3: 2013 :: : :::: :: |---|---|---|---|---|---|---|---| 50 = week 50 s 4 3 52 = week 52 |---|---|---|---|---|---|---|---| * lot number lot number to use all characters in marking |---|---|---|---|---|---|---|---| | bottom mark pin 1 indicator (dot) no bottom mark top mark seal year | seal week y = seal year ww = seal week | | | 6: 2006 0: 2010 02 = week 2 |---|---|---|---|---|---|---|---| 7: 2007 1: 2011 04 = week 4 a t m l h y w w 8: 2008 2: 2012 :: : :::: : |---|---|---|---|---|---|---|---| 9: 2009 3: 2013 :: : :::: :: s 4 3 50 = week 50 |---|---|---|---|---|---|---|---| 52 = week 52 lot number |---|---|---|---|---|---|---|---| * | bottom mark pin 1 indicator (dot) no bottom mark
22 5107e?sflsh?8/07 at25fs040 7. package information 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. color a do s pring s , co 8 0906 title drawing no. r rev. note: 10/7/0 3 8s 1 , 8 -le a d (0.150" wide body), pl as tic g u ll wing s m a ll o u tline (jedec s oic) 8s 1 b common dimen s ion s (unit of me asu re = mm) s ymbol min nom max note a1 0.10 ? 0.25 the s e dr a wing s a re for gener a l inform a tion only. refer to jedec dr a wing m s -012, v a ri a tion aa for proper dimen s ion s , toler a nce s , d a t u m s , etc. a 1. 3 5 ? 1.75 b 0. 3 1 ? 0.51 c 0.17 ? 0.25 d 4. 8 0 ? 5.00 e1 3 . 8 1 ? 3 .99 e 5.79 ? 6.20 e 1.27 b s c l 0.40 ? 1.27 ? 0 ? 8 ? top view end view s ide view e b d a a1 n e 1 c e1 l
23 5107e?sflsh?8/07 at25fs040 8y7 ? ut sap 1150 e. cheyenne mtn. blvd. colorado springs, co 80906 title drawing no. r rev. 8y7 , 8-lead (6.00 x 4.90 mm body) ultra-thin soic array package (utsap) y7 b 8y7 10/13/05 common dimensions (unit of measure = mm) symbol min nom max note a ? ? 0.60 a1 0.00 ? 0.05 d 5.80 6.00 6.20 e 4.70 4.90 5.10 d1 3.30 3.40 3.50 e1 3.90 4.00 4.10 b 0.35 0.40 0.45 e 1.27 typ e1 3.81 ref l 0.50 0.60 0.70 d1 pin 1 id e1 l b e1 e pin 1 index area a e d a1 a
24 5107e?sflsh?8/07 at25fs040 8. revision history doc. rev. date comments 5107e 8/2007 added die sales info to features modified order code table updated to new template added parts marking tables 5107d 9/2006 implemented revision history.
5107e?sflsh?8/07 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support s_eeprom@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2007 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others, ar e registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others.

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